A clock signal may be distributed throughout a processor to facilitate the processor's operation. For example, state elements located at different points in the processor die may function synchronously by operating in accordance with the clock signal.
FIG. 1 is a block diagram of a traditional clock signal system 100. A core Phase-Locked Loop (PLL) unit 10 receives a reference clock signal and generates a clock signal (e.g., having a frequency of N* the frequency of the reference clock signal) that is provided to core state elements 30 via a core clock network 20 (e.g., a clock distribution tree). The output of the core clock network 20 is also provided back to the core PLL unit 10 through a divider 40 (e.g., a device that divides the feedback signal by N).
The reference clock signal is also provided to an Input Output (IO) PLL unit 110. The IO PLL unit 110 generates a clock signal (e.g., having a frequency of M* the frequency of the reference clock signal) that is provided to IO state elements 130 via an IO clock network 120. The output of the IO clock network 120 is also provided back to the IO PLL unit 110 through a divider 140 (e.g., a device that divides the feedback signal by M). The IO state elements 130 can then exchange information with the system and the core state elements 30. Note that the operation of the IO state elements 130 will be synchronized with the operation of the core state elements 30 (e.g., because each is receiving a clock signal that was generated based on the reference clock signal).
Several problems may arise, however, in the traditional clock signal system 100. For example, the core PLL unit 10 and the IO PLL unit 110 are powered by a fixed analog power supply such that once lock is achieved the core and IO clock frequencies will remain substantially fixed. When a large, sudden current requirement occurs, the on-die voltage provided to the core state elements 30 will “droop” (e.g., for a few nanoseconds) while the core PLL unit 10 continues to generate a clocks signal having a fixed frequency. Note that other voltage droop events may last even longer. To ensure that the processor functions during these droop events, a high voltage margin may be provided for the core state elments30 even during normal operation (e.g., when there is no voltage droop). That is, the processor is designed to operate at both the highest specified frequency and at the lowest potential voltage simultaneously.
Since power has a quadratic dependence on voltage, a significant amount of power may be wasted during normal operation to ensure functionality during the infrequent voltage droops. Moreover, as processor speed and integration increases, the amount of power that is required may become a limiting factor. For example, the costs of designing and cooling a processor that consumes a significant amount of power may become impractical.